About

My name is Tom Spink, and I’m a lecturer in the School of Computer Science at the University of St Andrews. Previously, I was a Senior Researcher in the School of Informatics at the University of Edinburgh, where I worked on the McDoC project with Björn Franke, and the PAMELA project with Michael O’Boyle.

I lead the AVISI (Architecture Virtualisation and Simulation) research group, which (as per its name) is interested in how we can efficiently virtualise and simulate computer architectures.

If you’re interested in studying for a PhD with me - get in touch!

Selected Publications

Fast and correct load-link/store-conditional instruction handling in DBT systems

In proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Dynamic Binary Translation (DBT) requires the implementation of load-link/store-conditional (LL/SC) primitives for guest systems that rely on this form of synchronization. When targeting e.g. x86 host systems, LL/SC guest instructions are typically emulated using atomic Compare-and-Swap (CAS) instructions on the host. Whilst this direct mapping is efficient, this approach is problematic due to subtle differences between LL/SC and CAS semantics. In this paper, we demonstrate that this is a real problem, and we provide code examples that fail to execute correctly on QEMU and a commercial DBT system, which both use the CAS approach to LL/SC emulation....

A retargetable system-level DBT hypervisor

In ACM Transactions on Computer Systems

System-level Dynamic Binary Translation (DBT) provides the capability to boot an Operating System (OS) and execute programs compiled for an Instruction Set Architecture (ISA) different to that of the host machine. Due to their performance-critical nature, system-level DBT frameworks are typically hand-coded and heavily optimized, both for their guest and host architectures. While this results in good performance of the DBT system, engineering costs for supporting a new, or extending an existing architecture are high....

Hardware accelerated cross-architecture full-system virtualization

In ACM Transactions on Architecture and Code Optimization (TACO)

Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. While hardware assistance for virtualization is supported by all major processor architectures, including Intel, ARM, PowerPC & MIPS, these extensions are targeted at virtualization of the same architecture, e.g. an x86 guest on an x86 host system. Existing techniques for cross-architecture virtualization, e.g. an ARM guest on an x86 host, still incur a substantial overhead for CPU, memory and I/O virtualization due to the necessity for software emulation of these mismatched system components....